Electronic desk top calculators have been changed in design due to the availability of MOS/LSI chips which allow the entire system to be embodied in only one or a small number of semiconductor devices. This technology permits large savings in manufacturing, labor and material costs and allows calculators to have operating functions not possible at reasonable cost in machines built from discrete devices or from large numbers of integrated circuits. A calculator system adapted to be implemented using only one MOS/LSI chip is set forth in copending application "Variable Function Calculator", Ser. No. 163,565 now abandoned, and replaced by Ser. No. 420,999, assigned to the assignee of this invention. A feature of the calculator disclosed in application Ser. No. 420,999 is the use of a random access memory array which is sequentially addressed to operate as a plurality of shift registers; this unit provides the main data registers in a space on the chip much less than needed for shift registers of conventional design. Another features of said application was the keyboard scanning technique.
The above referenced application, Ser. No. 360,984, provided an improved electronic calculator system adapted to be implemented in MOS/LSI technology of using several semiconductor chips or wafers. An expandable system included optional program memory arrays, external data registers and an output printer chip utilizing novel addressing techniques. Other features included use of the sequentially addressed memory set forth in copending application Ser. No. 420,999 with a timing arrangement in such a manner that auxiliary timing generators were not needed, and a keyboard interface register was provided which stored encoded keyboard and timing information for subsequent entry into the data registers or for selecting an address for the program memory. Application Ser. No. 360,984 disclosed the desirability of having a ROM/register chip and the advantages flowing therefrom.
It is therefore an object of the present invention to provide in a calculator system peripheral memory on a semiconductor chip which is addressed by a primary system. It is another object of the present invention to provide a peripheral data memory which is addressed by strategic communication of only a single flag signal coordinated with system status and timing signals. It is yet another object to provide a calculator system having a primary semiconductor chip set providing primary memory and computation functions and another chip interfacing therewith providing additional memory capacity and further to provide the method of addressing the chip by communicating a flag signal thereto at a selected system time prior to the data exchange on data lines.
It is yet another object to provide a method of addressing an suxiliary chip providing a plurality of functions in a multi-chip calculator system whereby the particular function supplied by the auxiliary chip is determined by communication of a flag signal to the auxiliary chip at a selected time in the system timing cycle.
Briefly and in accordance with the present invention, a calculator system is provided on a plurality of semiconductor integrated circuit chips with at least one of the chips providing peripheral instruction word and data storage. A flag signal at a preselected subcycle system time is generated on one of a primary set of chips and communicated in relationship to the system cycle timing to the peripheral chip for effecting addressing. Fifteen states are provided in the timing cycle which provides up to fifteen functions to be selected for execution on the peripheral chip. Communication of the flag signal during one state of the timing cycle indicates that data is to be written into a first register, and communication during a second state indicates that data is to be written into a second register and so on. Communication of the flag signal during another state of the timing cycle indicates that data is to be read from one of the registers, and communication of the flag signal at a subsequent state indicates that data is to be read from another register, and so forth, with provision for clearing all registers.